The following applications, including this one, are being filed concurrently, and the disclosure of the other applications are incorporated by reference into this application in their entirety for all purposes:
U.S. patent application Ser. No. 09/410,633, entitled xe2x80x9cAN INTEGER INSTRUCTION SET ARCHITECTURE AND IMPLEMENTATIONxe2x80x9d;
U.S. patent application Ser. No. 09/690,340, entitled xe2x80x9cA METHOD FOR LOADING AND STORING DATA IN A COMPUTER SYSTEMxe2x80x9d;
U.S. patent application Ser. No. 09/411,600, entitled xe2x80x9cA FLOATING POINT INSTRUCTION SET ARCHITECTURE AND IMPLEMENTATIONxe2x80x9d.
U.S. patent application Ser. No. 09,410,675, entitled xe2x80x9cA METHOD FOR ENCODING COMPUTER INSTRUCTION DATA FIELDxe2x80x9d.
The present invention relates generally to computer instruction set architectures, and particularly to the setting of selected operand fields.
In the past decade RISC (Reduced Instruction Set Computer) architectures, in which each instruction is ideally performed in a single operational cycle, have become popular. RISC architecture computers present several advantages over standard architecture computers. For instance, RISC instruction sets are capable of much higher data processing speeds due to their ability to perform frequent operations in shorter periods of time. The RISC devices began with 16-bit instruction sets, and grew to 32-bit instruction set architectures.
Pipelining techniques have been used in conjunction with RISC architectures to increase data throughput. Pipelining brought the need for data dependency checking; where the output of one instruction is the expected input into a following instruction. In some cases, instructions are divided into monadic (single source) and dyadic (dual source) instructions, each having its own unique dependency logic.
In addition to the complexities introduced by pipelining, applications have also contributed to the increasing complexity of RISC architectures. Frequently used constants, such as zero, can be set in different places from different sources.
Thus there is need for simplifying dependency logic without adding additional complexities to the hardware. In addition, there is a need to have a centralized, known source for zero to simplify the use of this frequently accessed constant.
According to the present invention, techniques for setting selected operand fields in pipelined architectures are provided. Methods and systems for efficiently selecting operand fields according to the present invention can be operative on a variety of computer architectures, including RISC architectures.
In a specific embodiment, the present invention provides a method for performing dependency checking on computer instructions in a pipeline of a computer system including determining if a first computer instruction has an opcode operating on only a first source operand. The computer instruction can have an opcode and a plurality of source operands, for example. Next, additional source operands can be replaced with the first source operand or the constant zero operand. Dependencies can be detected between the operands in the computer instruction and operands in other computer instructions in the pipeline. In a present embodiment, detecting can use the dyadic dependency checking for monadic instructions.
In another embodiment, the present invention provides a computer system for executing a computer instruction in a pipeline. The system can include a memory containing the computer instruction. The computer instruction can have a plurality of data fields, for example. A register that can return all zeros and a computer processor for executing the computer instruction stored in memory can also be part of the computer system. In a presently preferable embodiment, the register can be a 64-bit read only register, for example. The computer system can place one operand into the register while executing the computer instruction, for example.
Numerous advantages are provided by select embodiments according to the present invention. Embodiments can provide for setting selected operand fields in pipelined instructions for select computer architectures. In some embodiments, dependency checking for pipelined instructions can be provided. Many embodiments can be operable with RISC type computer architectures. Select embodiments can provide a standard hardware source for frequently used constant values and the like.
These and other advantages and features of the present invention will become apparent to those skilled in this art upon a reading of the following detailed description, which should be taken in conjunction with the accompanying drawings.